1. Field of the Invention
The invention relates to a vertical transistor structure in which an epitaxial layer is formed on the semiconductor substrate and a vertical transistor is formed in an epitaxial tray.
2. Description of the Prior Art
Such a transistor structure is called a vertical pnp-transistor. Among other things, vertical transistors have the advantage over lateral transistors in that the current does not flow at the surface and therefore, surface effects have only little influence on the transistor function. Lateral transistors require a relatively large base width due to their design, in which an emitter zone is surrounded by a collector ditch separated by the base region, because of undesired underetching and widening of fusion zones. Connected therewith is a higher gain factor only for small currents, while for larger currents, the gain decreases greatly. Vertical transistors, on the other hand, have a smaller base width and a high current gain which is less current dependent, as well as a current carrying capacity layer by about two orders of magnitude.
According to the state of the art, a vertical pnp-transistor is formed in an epitaxial tray on the semiconductor substrate which is insulated from other regions of the semiconductor crystal by insulating walls. In the interior between the insulating walls there are two buried layers, of which the first, n-doped one forms against the semiconductor substrate an insulating tray for the second p-doped buried layer which extends from the first buried layer into the epitaxial layer. Approximately centrally above the second buried layer there is a p-doped connecting zone which forms the emitter. The emitter connection zone surrounds a likewise p-doped ditch which extends down into the second buried layer and serves together with it as a collector which has a connecting zone in the region of the ditch. An n-doped base connection zone is arranged between the emitter connection zone and the collector ditch.
A vertical pnp-transistor constructed in this manner needs comparatively much larger space compared to npn-transistors, because within the tray formed by insulating walls, a collector ditch exists which surrounds the emitter connection zone.